Radiation tolerant single board computers (SBCs) integrate system on chips (SOCs), designed for earth based applications, and implement system level fault tolerance mechanisms to allow these SOCs to be usable in space applications. These radiation tolerant SBCs implement a number of communication interfaces on custom made application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). The SOCs typically provide some type of shared parallel bus to enable onboard data communication with peripheral ASICs or FPGAs implementing such interfaces. The data bandwidth of the shared bus must be divided between all the connected peripheral interfaces and ASICs or FPGAs. This can lead to throughput and latency performance issues.
SpaceWire (SpW) is a spacecraft communication network based in part on the IEEE 1355 standard of communications. Various devices used during spaceflight need to be connected to SpaceWire subsystems or networks. For high-bandwidth input/output (I/O) interfaces, such as SpaceWire interfaces, it is desirable to use dedicated point-to-point I/O interfaces on SOCs. With commercial SOCs, these point-to-point interfaces typically support Ethernet (IEEE 802.3) protocols. However, commercial SOC processors do not directly support the SpaceWire interfaces required for space applications, and include a limited set of interface choices for connecting SpaceWire devices. The SOC interfaces conventionally used for SpaceWire connectivity suffer from either high complexity or lower-than-required performance. While prior approaches have demonstrated the feasibility of bridging Ethernet I/O to SpaceWire at the physical (PHY) interface layer, the lack of radiation-tolerant PHY devices, as well as the added cost, complexity, and power, makes such approaches impractical.